FIGS. 1A to 1E illustrate the various steps of one mode of fabricating an SOI type substrate, which is known in the art.
As shown in FIGS. 1A and 1B, the known method consists of oxidizing a source substrate Sou to form a layer of oxide Oxy on a surface of Sou. The method then provides for atomic species implantation in Sou to define an active layer Cact. Oxide layer Oxy is generally fairly thick, of the order of 150 nanometers (nm).
After bonding a surface of oxide Oxy to a support substrate Sup (FIG. 1C), and detaching a remainder of source substrate Sou (FIG. 1D), a composite substrate is obtained comprising oxide layer Oxy interposed between support substrate Sup and an active layer Cact. As illustrated in FIGS. 1C and 1D, oxide layer Oxy has a contact interface I1 with support substrate Sup. Oxide layer Oxy also has a contact interface I2 with active layer Cact.
In some embodiments, a layer may be formed on an exposed surface of the composite substrate obtained, which layer is intended to protect the exposed surface of the upper during finishing heat treatments carried out on the substrate. Substrate Sup is covered with a protective layer Cpr arranged adjacent active layer Cact. An interface I3 is interposed between protective layer Cpr and active layer Cact.
As known in the art, an interface can comprise a trap, wherein a trap has a capacity to retain or release charge carriers at interfaces. A trap can have an extremely deleterious impact on electrical properties of any future electronic components produced on the composite substrate. The density of traps at an interface (hereinafter the “DIT value”) is expressed as the number of traps/eV·cm2. The higher the DIT value, the worse the electrical properties of the substrate.
For example, a value of 1012·eV−1·cm−2 considered a high value and can correspond to poor electrical properties for the substrate. Currently, the best DIT values obtained are of the order of 1010·eV−1·cm−2 for interfaces between very good quality oxides, known as “gate oxides”, and their support. Such oxides are found, for example, in transistors, memories, capacitors, and other types of components forming integrated circuits.
The prior art includes methods that can improve or reduce DIT values at certain interfaces of a composite substrate. One of the known methods is Forming Gas Anneal (FGA), which consists of carrying-out a repair/recovery heat treatment of interfaces at a low temperature, on the order of 450° C., in an atmosphere containing hydrogen and a neutral gas.
However, when such a method is carried out at 450° C., improvement to the DIT value is exerted solely on interface I3 between protective layer Cpr and active layer Cact. The improvement in DIT value exerted by FGA treatment on interfaces I1 and I2 is very slight or is none at all. Thus, the FGA treatment method loses effectiveness at each encountered interface. Thus, FGA treatment is relatively ineffective for deep-lying interfaces.
Another method known in the art, consists of carrying out an annealing heat treatment at a high temperature, i.e., above 900° C. or even above 1000° C. Such a treatment may improve the DIT value at the interface I2, but cannot be applied to a certain number of substrates.
This treatment cannot be applied to certain structures formed by bonding, or to composite substrates containing materials that are unstable at high temperature, such as germanium (Ge) or strained Si (sSi), for example. This treatment also cannot be applied to substrates formed from a plurality of materials having significant differences in thermal expansion coefficient (silicon on quartz or SOQ, for example) or substrates containing elements that should not be allowed to diffuse, for example doping profiles or a structure including a metallic ground plane. Thus, it is not possible to apply any DIT improvement treatments employing high temperatures to these types of structures.
In addition, it is also necessary to use for composite substrate fabrication, bonding techniques which do not necessitate high temperature heat treatments. Suni et al, “Effect of plasma activation on hydrophilic bonding of Si and SiO2,” Electrochemical Society Proceedings, Volume 2001-27, pp 22-30, describe a technique consisting of preceding the step of bringing the surfaces to be bonded into intimate contact, by a step of plasma activation of at least one of the surfaces to be bonded, namely that of support Sup and/or of source Sou. A high bonding energy is thus obtained at interface I1, close to 1 J/m2 (joule/meter2), even after an anneal at 200° C. for just 1 hour. However, plasma activation deteriorates electrical characteristics of interface I1, and in particular DIT values of interface I1, in a fairly significant manner.
An article by K. Schjölberg-Henriksen et al, “Oxide charges induced by plasma activation for wafer bonding,” Sensors and Actuators A 102 (2002), 99-105, describes the negative effect of plasma activation on the electrical properties of substrates. This article also shows that it is possible to correct the deleterious effects of plasma activation on electrical properties of substrates by a subsequent FGA type annealing treatment. Using the methods described in the article, a good quality oxide is produced on a silicon substrate, where the DIT value of interface I1 is of the order of several 1010·eV−1 cm−2 after plasma activation, but unfortunately the bonding forces after the FGA treatment are reduced by more than 50%.
In composite substrates, it is important to produce a strong bond in a composite structure, for example, when subsequent thinning of a constituent layer is envisaged, for example, to avoid problems with non transferred zones. Thus improvements in electrical properties of composite substrates, for example, DIT values, while maintaining a strong bond is a composite structure are desirable and necessary. The present invention now provides herein methods and systems for obtaining such improvements.